1. Field of the Invention
The present invention generally relates to a semiconductor device and method therefor, and more particularly to a structure and method of ultra-small (e.g., within a range of about 10 nm to about 20 nm) grain size polysilicon.
2. Description of the Related Art
State-of-the-art complementary metal oxide semiconductor (CMOS) gates are beginning to target 30 nm lengths. Typical polysilicon grain sizes are in the 50 nm range (e.g., see S. Wolf, Silicon Processing for the VLSI Era, Vol. 2, Lattice Press, 1990; U.S. Pat. No. 6,294,442).
However, this 50 nm grain size creates many problems including that the polysilicon is more bamboo-like along the gate lines, and conductivity/resistivity becomes more sensitive to grain size at this nano-scale level (e.g., conductivity/resistivity tracks with grain size).
More specifically, assume that one has a 30 nm grain size and a 30 nm gate polysilicon is etched so that across the width there is one grain (e.g., there is a single crystal along the width). The length of the gate may be microns long. Hence, there is a single crystal all along the gate in a cross-section. Thus, a ladder structure (e.g., a “bamboo-like” structure) is formed in which the width is very small, but the length may be very long. This is problematic because the resistance would be very large otherwise.
Another problem is that the diffusion of dopants in these “large-grain” polysilicon gates will probably be mostly through lattice diffusion (similar to that of crystalline silicon) which is relatively slow (e.g., typically about a factor of 10 slower than diffusion for polysilicon) and sufficient dopant may not reach the polysilicon/oxide interface, where dopant is also needed to prevent polysilicon depletion effects.
Further, one may have to increase thermal budgets enormously (e.g., to 1050° C. for about 5 seconds or the like, depending upon the dopants used, etc.) to cause dopants to reach the polysilicon/oxide interface and recoup this depletion loss, which then impacts channel doping adversely.
Therefore, for small gate lengths, it is very useful to have polysilicon with a much smaller average grain size of 10–20 nm. However, prior to the present invention, such has not been achieved.
That is, it is well known that polycrystalline grain size may somewhat correlate with film thickness, and given that the typical gate stack thicknesses are in the 100 nm range, it is difficult to limit the grain size to the 10–20 nm range.
Indeed, all previous methods at controlling the average grain size through various deposition conditions have consistently yielded best defect-free material only in the ˜50 nm average grain size range.
Thus, prior to the present invention, there has been no method for making small nano-scale grained polysilicon with a concomitant structure that goes along with it.